The present invention relates to an apparatus in a digital video tape recorder (DVTR) for detecting a sync signal in digital data. More particularly, the present invention relates to an apparatus for the detection of a sync signal in serial data which has been reconstituted from parallel data. Such an apparatus facilitates recovery from the slip-off of synchronization of bits, and enables the detection of sync patterns with less circuitry than that of a sync detection system operating at a parallel data rate.
U.S. Pat. No. 4,275,466 discloses a sync detection scheme in which circuitry operates at a serial clock rate. Meanwhile, U.S. Pat. No. 4,879,731 discloses a system for detecting a sync signal in parallel data converted from serial data.
FIG. 1 is a block diagram of conventional sync detection circuitry operating at a serial data rate. FIG. 2 is a waveform diagram for explaining the operation of the system shown in FIG. 1. FIG. 3 is a block diagram of another conventional sync detection system operating at a parallel data rate.
Referring to FIG. 1, data signal SD is applied to a predetermined sync pattern matching means 15 operative to detect when a bit pattern in a shift register corresponds to a predetermined sync bit pattern that is supposed to be recorded once in each of the successive blocks of N bits recorded on a recording medium. The sync pattern matching means 15 generates a detected sync signal Si whenever such a correspondence is detected. A pulse signal PG indicates the reading of a track has begun, and a signal SM is a search-mode setting signal. The signal SM attains a high level upon receipt of the signal PG, and then attains a low level once the signal Si is generated to thereby search an initial sync signal Sync.
The sync signal Sync serves as a clear signal to a counter 22 so that the counter 22 is cleared by an output of an OR gate 18 each time a sync signal is generated. Once cleared, the counter 22 continues counting reference pulses PR. The counter 22 repeatedly counts the output of the OR gate 18 from 0 to Nxe2x88x921 in response to the pulses of reference pulse signal PR, and an AND gate 23 supplied a counted sync signal S1. That is to say, the counter 22 counts the output of the OR gate 18 to produce a sync signal, and when the count of N counter 22 attains a value of Nxe2x88x921, the AND gate 23 supplies a counted sync signal S1. CM indicates a check mode signal. The CM signal becomes a high signal when the detected sync signal Si does not correspond to the counted sync signal S1, and attains a low level every time an output Sc of a comparator 35 is produced. When all the signals Si, CM and Sc attain a high level, they are recognized as sync signals.
This system requires proper re-alignment of the data for the recovery from the slip-off synchronization of bits, but only performs the delay propagation of serial data. This gives rise to a disadvantageous problem in subsequent data processing.
FIG. 3 is a block diagram of a sync detection system performed at a parallel data rate. This system includes a converting means 51 that receives serial digital data and a serial clock signal from a reproducing head of a digital tape recorder. The converting means 51 converts this data into a parallel form, and generates a parallel clock signal that is provided to other parts of the circuit.
It is assumed that a sync pattern of this type may have any one of eight different positions or alignments in the parallel data stream. A detecting means 52 detects the sync pattern in one of these eight alignments. Whenever a sync pattern is detected, the detecting means 52 produces a sync signal and a position signal indicating the particular alignment detected. A comparing means 52 calculates the difference between the situation where a sync pattern is detected and where it is expected on the basis of the previous sync pattern. This system is different from the one operating at a serial data rate in comparing the actual position with an expected position indicated by an expected position signal. This parallel-data sync detection needs N comparators (not illustrated) in the comparing means 53 in the situation where Mxe2x88x92N modulation-demodulation is being performed, and when a detected sync signal is generated from one of the N comparators, re-aligned data and a final sync signal are produced by means of an encoder (not illustrated) and a decoder (not illustrated).
When a sync slip occurs before and after a position at which a sync signal is detected, by using a first signal generating means 54 and a third signal generating means 56, a SYNC-IN-WINDOW signal is moved forward and backward. The decoder of the comparing means 53, the first signal generating means 54, and the third signal generating means 56 should employ N multiplexers, an adder (not shown), and a memory (not shown), respectively, which results in a complicated circuitry arrangement.
In the sync detection circuit operating at a parallel data rate, the sync patterns in a data bit stream that are recorded in serial form become an important factor, and may be impaired by damage to a tape, degradation of signals, or errors in the rotational speed of drums, all of which make sync detection difficult. Besides, there may occur errors in data patterns, as well as a lack of coincidence between clock signals of sync patterns. The serial-data sync detection has a problem in that synchronization errors adversely affect the correction of sync slip in bit positions.
The sync detection system performing at a parallel data rate has a first step for converting the incoming serial data to parallel data without regard to proper alignment. Sync detection is then performed upon the parallel data at the parallel data rate, and the parallel data is shifted into its original alignment, using the position of the detected sync patterns as a guide. Such a sync detection scheme reduces the need for high speed logic and facilitates correction for the slip-off of the synchronization of bits. This scheme, however, is difficult to carry out in large scale integration.
There is a need for an apparatus in a digital video tape recorder according to which sync detection and data alignment may be performed at a serial clock rate, thus correcting synchronization errors using a predetermined window situated around the expected position of the sync signal, and providing a proper response to the displacement or absence of sync signals, while at the same time, reducing circuitry as compared to that of the sync detection system operating at a parallel data rate.
With this in mind, the present invention relates to an apparatus in a digital video tape recorder for detecting a sync signal in digital data, comprising: data restoring means for producing serial data and a serial clock signal received from a reproducing head of the digital video tape recorder; servo means for producing a head switching pulse and a super-video home system (S-VHS)/video home system (VHS) discriminating signal; identification detecting means for producing a signal indicative of an end of reading one segment of tracks; and sync signal detecting means, responsive to each signal produced by the aforementioned means, for determining correspondence in sync patterns even in a case where not all corresponding bits coincide with one another, for removing erroneously detected sync patterns using a window situated around a position at which a sync signal is produced, and for detecting a sync signal.